Introduction to Digital Design and Integrated Circuits
Course Outline
- Ask questions on our Ed forum for this semester.
- Homeworks will be posted as links in the outline below.
- Please submit completed homework via Gradescope.
Lecture Playlist
NEW Lab/OH Queue Form
Lab/OH Queue Form
| Week | Date | Lecture Topic | Discussion | ASIC Lab | FPGA Lab | Homework |
|---|---|---|---|---|---|---|
| 1 | 1/17 | Class Organization & Introduction to Course Content (slides) (recording) | Discussion 1 (slides) (worksheet) | No Lab | No Lab | Homework 1 (Solution) |
| 2 | 1/22 | Design Alternatives & ASIC Flow(slides) (recording) | Discussion 2 (slides) (worksheet) (solutions) | Lab 1 | Lab 1 | Homework 2 (solutions) |
| 1/24 | Verilog Part 1 (slides) (recording) | Verilog Review | ||||
| 3 | 1/29 | Verilog Part 2 (slides) (recording) | Discussion 3 (slides) (worksheet) (solutions) | Lab 2 | Lab 2 | Homework 3 (Solutions) |
| 1/31 | FPGA Architecture (slides) (recording) | |||||
| 4 | 2/5 | Combinational Logic & Boolean Algebra (slides) (recording) | Discussion 4 (slides) (worksheet) (solutions) | Lab 3 | Lab 3 | Homework 4 (solution) |
| 2/7 | Finite State Machines 1 (slides) (recording) | |||||
| 5 | 2/12 | Finite State Machines 2 (slides) (recording) | Discussion 5(slides)(worksheet) (solutions)(recording) | Lab 4 | Lab 4 | Homework 5 (solution) |
| 2/14 | CMOS Circuits 1 (slides) (recording) | |||||
| 6 | 2/19 | Presidents’ Day | Discussion 6(slides) (worksheet) (solutions) (recording) | Lab 5 | Homework 6(solution) | |
| 2/21 | CMOS Circuits 2 (slides) (recording) | |||||
| 7 | 2/26 | Circuit Timing Part 1 (slides) (recording) | Discussion 7(slides) (worksheet) (solutions) (recording) | Lab 6 | Lab 5 | Homework 7 (solutions) |
| 2/28 | Circuit Timing Part 1 Cont. (slides) (recording) | |||||
| 8 | 3/4 | Circuit Timing Part 2 (slides) (recording) | Discussion 8(concept review)(problem review)(concept review recording 1)(concept review recording 2) | Lab 6 | ||
| 3/6 | RISC-V Microarchitecture and Implementation (slides) (recording) | |||||
| 9 | 3/11 | Midterm Review (slides) (recording) | Discussion 9(slides) | ASIC Project | FPGA Project | |
| 3/12 | Midterm 7-10pm | Midterm(solutions) | ||||
| 3/13 | RISC-V Part 2 (slides) (recording) | |||||
| 10 | 3/18 | Memory Blocks 1 (slides)(recording) | Discussion 10(slides) | Checkpoint 1 | Checkpoint 1 | Homework 8 (solutions) |
| 3/20 | Memory Blocks 2 (slides) (recording) | |||||
| 11 | 3/25 | Spring Break | ||||
| 3/27 | Spring Break | |||||
| 12 | 4/1 | Memory Blocks 2 (slides) (recording) | Discussion 11(slides) | Checkpoint 2a | Homework 9 (solutions) | |
| 4/3 | Power and Energy (slides) (recording) | |||||
| 13 | 4/8 | Parallelism (slides) (recording) | Discussion 12(slides) | Checkpoint 2 | Checkpoint 2b | Homework 10(solutions) |
| 4/10 | List Processor Example Design (slides) (recording) | |||||
| 14 | 4/15 | Adders (slides) (recording) | Discussion 13(slides) | Homework 11(solutions) | ||
| 4/17 | Multipliers & Shifters (slides) (recording) | |||||
| 15 | 4/22 | Guest Lecture: Hardware Verification | Final Discussion Problems(slides) | Checkpoint 3 | Checkpoint 3 | |
| 4/24 | Clock and Wrap-up (slides) (recording) | |||||
| 16 | 4/29 | RRR No Lecture | ||||
| 5/1 | RRR No Lecture | Final Checkoff | ||||
| FINAL | 5/7 | Final Exam 11:30A - 2:30P | Report due midnight 5/8 |
Lectures, Labs, Office Hours
| Content | Days | Times | Location | Staff |
|---|---|---|---|---|
| Lectures | Mon, Wed | 2:00 pm - 3:30 pm | Soda 306 | John Wawrzynek |
| Discussion | Fri | 10:00 am - 11:00 am | Cory 540AB | Justin Kalloor |
| Fri | 3:00 pm - 4:00 pm | Wheeler 108 | Kevin Anderson | |
| Fri | 4:00 pm - 5:00 pm | Hearst Mining 310 | Kevin Anderson | |
| ASIC Lab | Tu | 11:00 am - 2:00 pm | Cory 111/117 | Kevin He |
| Tu | 2:00 pm - 5:00 pm | Cory 111/117 | Kevin Anderson | |
| FPGA Labs | Mon | 8:00 am - 11:00 am | Cory 111/117 | Daniel Endraws |
| Mon | 11:00 am - 2:00 pm | Cory 111/117 | Daniel Endraws | |
| Tu | 8:00 am - 11:00 am | Cory 111/117 | Rohit Kanagal | |
| Mon | 5:00 pm - 8:00 pm | Cory 111/117 | Dhruv Vaish | |
| Office Hours | Mon | 3:30 pm - 4:30 pm | 631 Soda | John Wawrzynek |
| Tu | 5:00 pm - 7:00 pm | Cory 111/117 | Kevin He | |
| Tu | 5:30 pm - 6:30 pm | Cory 111/117 | Allen Chen | |
| Wed | 4:30 pm - 6:30 pm | Cory 111/117 | Dhruv’s OH | |
| Thurs | 9:00 am - 11:00 am | Cory 111/117 | Daniel Endraws | |
| Thurs | 4:00 pm - 6:00 pm | Cory 111/117 | Kevin Anderson | |
| Tu | 7:00 pm - 8:00 pm | Cory 111/117 | Rohit Kanagal | |
| Fri | 11:00 am - 12:00 pm | Cory 111/117 | Justin Kalloor | |
| Fri | 12:00 pm - 2:00 pm | Cory 111/117 | Reuben Thomas |
Discussions, Homework
- Conceptual and homework questions should be directed to Ed forum for this semester.
- Homeworks will be posted as links in the outline, available in PDF format.
- Please submit completed homework via Gradescope. Homework will be released on Fridays before midnight, and will be due on the Monday 10 days later.
Staff
 |
John Wawrzynek | johnw at berkeley dot edu |
 |
Kevin Anderson (Discussion, HW, ASIC Lab) |
kevinand at berkeley dot edu |
 |
Justin Kalloor (Discussion & HW) |
jkalloor3 at berkeley dot edu |
 |
Dhruv Vaish (FPGA Lab) |
dvaish at berkeley dot edu |
 |
Daniel Endraws (FPGA Lab) |
daniel.endraws at berkeley dot edu |
 |
Kevin He (ASIC Lab) |
kevinjhe at berkeley dot edu |
 |
Rohit Kanagal (FPGA Lab) |
rkanagal at berkeley dot edu |
 |
Reuben Thomas (Reader) |
reubenkthomas at berkeley dot edu |
 |
Allen Chen (Reader) |
jiyangchen at berkeley dot edu |
Resources
- RISC-V Green Card
- 61C Reference
- IEEE 1364-2005 Verilog-Standard
- EECS151 Register Library
- Online Verilog Simulator (edaplayground)
- LTspice Tutorial
- Verilog FSM Review
- Ready-Valid Interface
- Always @ Blocks
- John W 61C Verilog Review
- Spring 24 Verilog Review
- Final Exam Topics
Previous Exams
- Spring 2023 midterm (blank) (solution)
- Spring 2021 midterm (blank)(solutions)
- Spring 2020 midterm (blank)(solutions)
- Spring 2023 final (blank) (solutions)
- Spring 2021 final (blank) (partial solutions)
- Spring 2020 final (blank) (solutions)
- Spring 2019 final (blank)
Homework Policy
Homework will be released on Fridays before midnight, and will be due on the Monday 10 days later. Homework will be challenging and graded for correctness.
Grading
Class
| Problem Sets | 30% |
| Participation | 5% |
| Midterm | 30% |
| Final | 35% |
ASIC Labs
| Lab Reports | 25% |
| Project | 75% |
FPGA Labs
| Lab Checkoffs + Reports | 25% |
| Project | 75% |
Cheating Policy
- If you turn in someone else’s work as if it were your own, you are guilty of cheating. This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
- Also, if you knowingly aid in cheating, you are guilty.
- We have software that compares your submitted work to others.
- However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
- Do not post your work on public repositories like github (private o.k.)
- If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat! If it is a midterm exam, final exam, or final project, you get an F in the class. All cases of cheating reported to the office of student conduct.